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Microchip Technology /ATSAMV71J19 /UART0 /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXRDY)RXRDY 0 (TXRDY)TXRDY 0 (OVRE)OVRE 0 (FRAME)FRAME 0 (PARE)PARE 0 (TXEMPTY)TXEMPTY 0 (CMP)CMP 0 (SWES)SWES 0 (CLKREQ)CLKREQ 0 (WKUPREQ)WKUPREQ

Description

Status Register

Fields

RXRDY

Receiver Ready
TXRDY

Transmitter Ready
OVRE

Overrun Error
FRAME

Framing Error
PARE

Parity Error
TXEMPTY

Transmitter Empty
CMP

Comparison Match
SWES

SleepWalking Enable Status
CLKREQ

Clock Request
WKUPREQ

Wake-Up Request

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data